SY_PD_SPARE=0, SY_LO_BUMP_RTLO_TX=0, SY_LO_BUMP_RTLO_FDBK=0, SY_LO_BUMP_RTLO_RX=0, SY_PD_PCH_SEL=0, SY_LO_DIAGSEL=0
RF Analog Synthesizer Control 1
SY_DIVN_SPARE | rmap_sy_divn_spare |
SY_FCAL_SPARE | rmap_sy_fcal_spare |
SY_LO_BUMP_RTLO_FDBK | rmap_sy_lo_bump_rtlo_fdbk[1:0] 0 (0): 1.045 V 1 (1): 1.084 V 2 (2): 1.097 V 3 (3): 1.10 V |
SY_LO_BUMP_RTLO_RX | rmap_sy_lo_bump_rtlo_rx[1:0] 0 (0): 1.051/1.037 V 1 (1): 1.082/1.075 V 2 (2): 1.092/1.088 V 3 (3): 1.098/1.094 V |
SY_LO_BUMP_RTLO_TX | rmap_sy_lo_bump_rtlo_tx[1:0] 0 (0): 1.071/1.065 V 1 (1): 1.092/1.090 V 2 (2): 1.099/1.098 V 3 (3): 1.10/1.1 V |
SY_LO_DIAGSEL | rmap_sy_lo_diagsel 0 (0): Diag disable 1 (1): Diag enable |
SY_LO_SPARE | rmap_sy_lo_spare[2:0] |
SY_LPF_FILT_CTRL | rmap_sy_lpf_filt_ctrl[2:0] |
SY_LPF_SPARE | rmap_sy_lpf_spare |
SY_PD_DIAGSEL | rmap_sy_pd_diagsel |
SY_PD_PCH_TUNE | rmap_sy_pd_pch_tune[1:0] |
SY_PD_PCH_SEL | rmap_sy_pd_pch_sel 0 (0): inverter based precharge 1 (1): resistor divider based precharge |
SY_PD_SPARE | rmap_sy_pd_spare[1:0] 0 (0): Default ; 1 (1): PD output is pulled down. |
SY_PD_VTUNE_OVERRIDE_TEST_MODE | rmap_sy_pd_vtune_override_test_mode |