Freescale Semiconductor /MKW21Z4 /XCVR_ANALOG_REGS /SY_CTRL_1

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Interpret as SY_CTRL_1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SY_DIVN_SPARE)SY_DIVN_SPARE 0 (SY_FCAL_SPARE)SY_FCAL_SPARE 0 (0)SY_LO_BUMP_RTLO_FDBK 0 (0)SY_LO_BUMP_RTLO_RX 0 (0)SY_LO_BUMP_RTLO_TX 0 (0)SY_LO_DIAGSEL 0SY_LO_SPARE 0SY_LPF_FILT_CTRL 0 (SY_LPF_SPARE)SY_LPF_SPARE 0 (SY_PD_DIAGSEL)SY_PD_DIAGSEL 0SY_PD_PCH_TUNE 0 (0)SY_PD_PCH_SEL 0 (0)SY_PD_SPARE 0 (SY_PD_VTUNE_OVERRIDE_TEST_MODE)SY_PD_VTUNE_OVERRIDE_TEST_MODE

SY_PD_SPARE=0, SY_LO_BUMP_RTLO_TX=0, SY_LO_BUMP_RTLO_FDBK=0, SY_LO_BUMP_RTLO_RX=0, SY_PD_PCH_SEL=0, SY_LO_DIAGSEL=0

Description

RF Analog Synthesizer Control 1

Fields

SY_DIVN_SPARE

rmap_sy_divn_spare

SY_FCAL_SPARE

rmap_sy_fcal_spare

SY_LO_BUMP_RTLO_FDBK

rmap_sy_lo_bump_rtlo_fdbk[1:0]

0 (0): 1.045 V

1 (1): 1.084 V

2 (2): 1.097 V

3 (3): 1.10 V

SY_LO_BUMP_RTLO_RX

rmap_sy_lo_bump_rtlo_rx[1:0]

0 (0): 1.051/1.037 V

1 (1): 1.082/1.075 V

2 (2): 1.092/1.088 V

3 (3): 1.098/1.094 V

SY_LO_BUMP_RTLO_TX

rmap_sy_lo_bump_rtlo_tx[1:0]

0 (0): 1.071/1.065 V

1 (1): 1.092/1.090 V

2 (2): 1.099/1.098 V

3 (3): 1.10/1.1 V

SY_LO_DIAGSEL

rmap_sy_lo_diagsel

0 (0): Diag disable

1 (1): Diag enable

SY_LO_SPARE

rmap_sy_lo_spare[2:0]

SY_LPF_FILT_CTRL

rmap_sy_lpf_filt_ctrl[2:0]

SY_LPF_SPARE

rmap_sy_lpf_spare

SY_PD_DIAGSEL

rmap_sy_pd_diagsel

SY_PD_PCH_TUNE

rmap_sy_pd_pch_tune[1:0]

SY_PD_PCH_SEL

rmap_sy_pd_pch_sel

0 (0): inverter based precharge

1 (1): resistor divider based precharge

SY_PD_SPARE

rmap_sy_pd_spare[1:0]

0 (0): Default ;

1 (1): PD output is pulled down.

SY_PD_VTUNE_OVERRIDE_TEST_MODE

rmap_sy_pd_vtune_override_test_mode

Links

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